Resume support for low-level uboot code, Version 5

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

Index: u-boot/cpu/arm920t/start.S
===================================================================
--- u-boot.orig/cpu/arm920t/start.S	2007-02-28 03:51:24.000000000 +0100
+++ u-boot/cpu/arm920t/start.S	2007-03-01 02:43:47.000000000 +0100
@@ -158,18 +158,68 @@
 	str	r1, [r0]
 # endif
 
+	/* default FCLK is 202 MHz ! */
+#define LOCKTIME	0x4c000000
+#define UPLLCON		0x4c000008
+//#define MPLLCFG		((0x90 << 12) + (0x2 << 4) + 0x2)
+#define MPLLCFG		((0x90 << 12) + (0x7 << 4) + 0x0)
+#define UPLLCFG		((0x78 << 12) + (0x2 << 4) + 0x3)
+	ldr	r0, =LOCKTIME
+	mov	r1, #0xffffff
+	str	r1, [r0]
+
+	ldr	r0, =UPLLCON
+	ldr	r1, =UPLLCFG
+	str	r1, [r0]
+
+	/* Page 7-19, seven nops between UPLL and MPLL */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	ldr	r1, =MPLLCFG
+	str	r1, [r0, #-4]		/* MPLLCON */
+
 	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
 	ldr	r0, =CLKDIVN
 	mov	r1, #3
 	str	r1, [r0]
+
+#if 1
+	/* enable uart */
+	ldr	r0, =0x4c00000c		/* clkcon */
+	ldr	r1, =0x7fff0		/* all clocks on */
+	str	r1, [r0]
+
+	/* gpio UART0 init */
+	ldr	r0, =0x56000070
+	mov	r1, #0xaa
+	str	r1, [r0]
+
+	/* init uart */
+	ldr	r0, =0x50000000
+	mov	r1, #0x03
+	str	r1, [r0]
+	ldr	r1, =0x245
+	str	r1, [r0, #0x04]
+	mov	r1, #0x01
+	str	r1, [r0, #0x08]
+	mov	r1, #0x00
+	str	r1, [r0, #0x0c]
+	mov	r1, #0x1a
+	str	r1, [r0, #0x28]
+#endif
+
 #endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #ifndef CONFIG_LL_INIT_NAND_ONLY
 	bl	cpu_init_crit
 #endif
-#endif
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 	adr	r0, _start		/* r0 <- current position of code   */
@@ -202,9 +252,33 @@
 
 #ifdef CONFIG_S3C2410_NAND_BOOT
 nand_load:
+	/* take sdram out of power down */
+	ldr	r0, =0x56000080		/* misccr */
+	ldr	r1, [ r0 ]
+	bic	r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
+	str	r1, [ r0 ]
+
+	/* ensure signals stabalise */
+	mov	r1, #128
+1:	subs	r1, r1, #1
+	bpl	1b
+
 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
 	bl	cpu_init_crit
 #endif
+#if defined(CONFIG_S3C2410)
+	/* ensure some refresh has happened */
+	ldr	r1, =0xfffff
+1:	subs	r1, r1, #1
+	bpl	1b
+
+	/* test for resume */
+	ldr	r1, =0x560000B4		/* gstatus2 */
+	ldr	r0, [ r1 ]
+	tst	r0, #0x02		/* is this resume from power down */
+	ldrne	pc, [r1, #4]		/* gstatus3 */
+#endif /* CONFIG_S3C2410 */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 	/* mov	r10, lr */
 
