beagleboard: added 2.6.29 kernel from OE

tested on B7 Signed-off-by: Marcin Juszkiewicz <marcin@buglabs.net>
2026-09-14 03:49:32 +02:00 · 2009-04-27 16:41:24 +02:00
parent d65be3dd2a
commit 0adc74b062
146 changed files with 156117 additions and 1 deletions
--- a/meta/packages/linux/linux-omap-2.6.29/beagleboard/ehci.patch
+++ b/meta/packages/linux/linux-omap-2.6.29/beagleboard/ehci.patch
@@ -0,0 +1,131 @@
+Index: git/arch/arm/mach-omap2/board-omap3beagle.c
+===================================================================
+--- git.orig/arch/arm/mach-omap2/board-omap3beagle.c
+++ git/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -154,6 +154,7 @@ static int beagle_twl_gpio_setup(struct
+ 	 * power switch and overcurrent detect
+ 	 */
+ 
+#if 0 /* TODO: This needs to be modified to not rely on u-boot */
+ 	gpio_request(gpio + 1, "EHCI_nOC");
+ 	gpio_direction_input(gpio + 1);
+ 
+@@ -163,7 +164,7 @@ static int beagle_twl_gpio_setup(struct
+ 
+ 	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+ 	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+-
+#endif
+ 	return 0;
+ }
+ 
+Index: git/arch/arm/mach-omap2/usb-ehci.c
+===================================================================
+--- git.orig/arch/arm/mach-omap2/usb-ehci.c
+++ git/arch/arm/mach-omap2/usb-ehci.c
+@@ -147,9 +147,11 @@ static void setup_ehci_io_mux(void)
+ 
+ void __init usb_ehci_init(void)
+ {
+#if 0 /* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+ 	/* Setup Pin IO MUX for EHCI */
+ 	if (cpu_is_omap34xx())
+ 		setup_ehci_io_mux();
+#endif
+ 
+ 	if (platform_device_register(&ehci_device) < 0) {
+ 		printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+Index: git/drivers/usb/host/ehci-omap.c
+===================================================================
+--- git.orig/drivers/usb/host/ehci-omap.c
+++ git/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,25 @@
+  *		to get the PHY state machine in working state
+  */
+ #define EXTERNAL_PHY_RESET
+#ifdef CONFIG_MACH_OMAP3_BEAGLE
+#define        EXT_PHY_RESET_GPIO_PORT2        (147)
+#else
+ #define	EXT_PHY_RESET_GPIO_PORT1	(57)
+ #define	EXT_PHY_RESET_GPIO_PORT2	(61)
+#endif
+ #define	EXT_PHY_RESET_DELAY		(10)
+ 
+#define PHY_STP_PULLUP_ENABLE           (0x10)
+#define PHY_STP_PULLUP_DISABLE          (0x90)
+
+ /* ISSUE2:
+  * USBHOST supports External charge pump PHYs only
+  * Use the VBUS from Port1 to power VBUS of Port2 externally
+  * So use Port2 as the working ULPI port
+  */
+#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
+#endif
+ 
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ 
+@@ -225,14 +234,43 @@ static int omap_start_ehc(struct platfor
+ 
+ #ifdef EXTERNAL_PHY_RESET
+ 	/* Refer: ISSUE1 */
+#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
+#endif
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
+	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ 	/* Hold the PHY in RESET for enough time till DIR is high */
+ 	udelay(EXT_PHY_RESET_DELAY);
+ #endif
+ 
+        /*
+         * The PHY register 0x7 - Interface Control register is
+         * configured to disable the integrated STP pull-up resistor
+         * used for interface protection.
+        *
+        * May not need to be here.
+         */
+        omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
+                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
+                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
+                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
+                (PHY_STP_PULLUP_DISABLE),
+                EHCI_INSNREG05_ULPI);
+
+        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
+
+        /* Force PHY to HS */
+        omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
+                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
+                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
+                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
+                (0x40),
+                EHCI_INSNREG05_ULPI);
+
+        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
+
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ 	if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +345,9 @@ static int omap_start_ehc(struct platfor
+ 	 * Hold the PHY in RESET for enough time till PHY is settled and ready
+ 	 */
+ 	udelay(EXT_PHY_RESET_DELAY);
+#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
+#endif
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+ 
+@@ -393,7 +433,9 @@ static void omap_stop_ehc(struct platfor
+ 
+ 
+ #ifdef EXTERNAL_PHY_RESET
+#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
+#endif
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+