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qemu: fix CVE-2020-27821
memory: clamp cached translation in case it points to an MMIO region (From OE-Core rev: 5240cce285d3baea513da0fc577b69e6f078a527) Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> (cherry picked from commit df92b3359743ed1837fa57df8035d121f5c5676b) Signed-off-by: Anuj Mittal <anuj.mittal@intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Sakib Sajal
committed by
Richard Purdie
Richard Purdie
parent
77de7815a7
commit
44de79f8f5
@@ -54,6 +54,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
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file://CVE-2021-3416_9.patch \
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file://CVE-2021-3416_9.patch \
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file://CVE-2021-3416_10.patch \
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file://CVE-2021-3416_10.patch \
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file://CVE-2021-20257.patch \
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file://CVE-2021-20257.patch \
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file://CVE-2020-27821.patch \
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"
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"
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UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
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UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
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143
meta/recipes-devtools/qemu/qemu/CVE-2020-27821.patch
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143
meta/recipes-devtools/qemu/qemu/CVE-2020-27821.patch
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@@ -0,0 +1,143 @@
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From 279f90a9ab07304f0a49fc10e4bfd1243a8cddbe Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Tue, 1 Dec 2020 09:29:56 -0500
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Subject: [PATCH 1/2] memory: clamp cached translation in case it points to an
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MMIO region
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In using the address_space_translate_internal API, address_space_cache_init
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forgot one piece of advice that can be found in the code for
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address_space_translate_internal:
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/* MMIO registers can be expected to perform full-width accesses based only
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* on their address, without considering adjacent registers that could
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* decode to completely different MemoryRegions. When such registers
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* exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
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* regions overlap wildly. For this reason we cannot clamp the accesses
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* here.
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*
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* If the length is small (as is the case for address_space_ldl/stl),
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* everything works fine. If the incoming length is large, however,
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* the caller really has to do the clamping through memory_access_size.
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*/
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address_space_cache_init is exactly one such case where "the incoming length
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is large", therefore we need to clamp the resulting length---not to
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memory_access_size though, since we are not doing an access yet, but to
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the size of the resulting section. This ensures that subsequent accesses
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to the cached MemoryRegionSection will be in range.
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With this patch, the enclosed testcase notices that the used ring does
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not fit into the MSI-X table and prints a "qemu-system-x86_64: Cannot map used"
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error.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Upstream-Status: Backport [4bfb024bc76973d40a359476dc0291f46e435442]
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CVE: CVE-2020-27821
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Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com>
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---
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softmmu/physmem.c | 10 ++++++++
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tests/qtest/fuzz-test.c | 51 +++++++++++++++++++++++++++++++++++++++++
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2 files changed, 61 insertions(+)
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diff --git a/softmmu/physmem.c b/softmmu/physmem.c
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index 3027747c0..2cd1de4a2 100644
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--- a/softmmu/physmem.c
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+++ b/softmmu/physmem.c
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@@ -3255,6 +3255,7 @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
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AddressSpaceDispatch *d;
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hwaddr l;
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MemoryRegion *mr;
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+ Int128 diff;
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assert(len > 0);
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@@ -3263,6 +3264,15 @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
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d = flatview_to_dispatch(cache->fv);
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cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
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+ /*
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+ * cache->xlat is now relative to cache->mrs.mr, not to the section itself.
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+ * Take that into account to compute how many bytes are there between
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+ * cache->xlat and the end of the section.
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+ */
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+ diff = int128_sub(cache->mrs.size,
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+ int128_make64(cache->xlat - cache->mrs.offset_within_region));
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+ l = int128_get64(int128_min(diff, int128_make64(l)));
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+
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mr = cache->mrs.mr;
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memory_region_ref(mr);
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if (memory_access_is_direct(mr, is_write)) {
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diff --git a/tests/qtest/fuzz-test.c b/tests/qtest/fuzz-test.c
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index 9cb4c42bd..28739248e 100644
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--- a/tests/qtest/fuzz-test.c
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+++ b/tests/qtest/fuzz-test.c
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@@ -47,6 +47,55 @@ static void test_lp1878642_pci_bus_get_irq_level_assert(void)
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qtest_outl(s, 0x5d02, 0xebed205d);
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}
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+/*
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+ * Here a MemoryRegionCache pointed to an MMIO region but had a
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+ * larger size than the underlying region.
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+ */
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+static void test_mmio_oob_from_memory_region_cache(void)
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+{
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+ QTestState *s;
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+
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+ s = qtest_init("-M pc-q35-5.2 -display none -m 512M "
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+ "-device virtio-scsi,num_queues=8,addr=03.0 ");
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+
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+ qtest_outl(s, 0xcf8, 0x80001811);
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+ qtest_outb(s, 0xcfc, 0x6e);
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+ qtest_outl(s, 0xcf8, 0x80001824);
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+ qtest_outl(s, 0xcf8, 0x80001813);
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+ qtest_outl(s, 0xcfc, 0xa080000);
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+ qtest_outl(s, 0xcf8, 0x80001802);
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+ qtest_outl(s, 0xcfc, 0x5a175a63);
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+ qtest_outb(s, 0x6e08, 0x9e);
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+ qtest_writeb(s, 0x9f003, 0xff);
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+ qtest_writeb(s, 0x9f004, 0x01);
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+ qtest_writeb(s, 0x9e012, 0x0e);
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+ qtest_writeb(s, 0x9e01b, 0x0e);
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+ qtest_writeb(s, 0x9f006, 0x01);
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+ qtest_writeb(s, 0x9f008, 0x01);
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+ qtest_writeb(s, 0x9f00a, 0x01);
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+ qtest_writeb(s, 0x9f00c, 0x01);
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+ qtest_writeb(s, 0x9f00e, 0x01);
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+ qtest_writeb(s, 0x9f010, 0x01);
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+ qtest_writeb(s, 0x9f012, 0x01);
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+ qtest_writeb(s, 0x9f014, 0x01);
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+ qtest_writeb(s, 0x9f016, 0x01);
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+ qtest_writeb(s, 0x9f018, 0x01);
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+ qtest_writeb(s, 0x9f01a, 0x01);
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+ qtest_writeb(s, 0x9f01c, 0x01);
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+ qtest_writeb(s, 0x9f01e, 0x01);
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+ qtest_writeb(s, 0x9f020, 0x01);
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+ qtest_writeb(s, 0x9f022, 0x01);
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+ qtest_writeb(s, 0x9f024, 0x01);
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+ qtest_writeb(s, 0x9f026, 0x01);
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+ qtest_writeb(s, 0x9f028, 0x01);
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+ qtest_writeb(s, 0x9f02a, 0x01);
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+ qtest_writeb(s, 0x9f02c, 0x01);
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+ qtest_writeb(s, 0x9f02e, 0x01);
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+ qtest_writeb(s, 0x9f030, 0x01);
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+ qtest_outb(s, 0x6e10, 0x00);
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+ qtest_quit(s);
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+}
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+
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int main(int argc, char **argv)
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{
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const char *arch = qtest_get_arch();
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@@ -58,6 +107,8 @@ int main(int argc, char **argv)
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test_lp1878263_megasas_zero_iov_cnt);
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qtest_add_func("fuzz/test_lp1878642_pci_bus_get_irq_level_assert",
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test_lp1878642_pci_bus_get_irq_level_assert);
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+ qtest_add_func("fuzz/test_mmio_oob_from_memory_region_cache",
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+ test_mmio_oob_from_memory_region_cache);
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}
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return g_test_run();
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--
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2.29.2
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