Various += were used, refactor these to be either = or .= depending on
usuage.
CONFLICTS should be '=', as no leading space is required and they are not
amending any other conflict settings.
The TUNE_CCARGS should be .= so that if the feature does not define a CCARG
blank spaces are not added to the CFLAGS. This is consistent to how the arm
tuning is implemented.
(From OE-Core rev: 78c38857486d3107ecd95d0ceefabcf5152c3928)
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
We want to allow no version to be configured. This should use the GCC default
which is the latest defined version, currently 11.0.
(From OE-Core rev: 0d1551dcc169f2d8dbfbe01b4f1f0ae3ce4770ed)
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Using microblazeeb breaks a number of autoconf recipes, including newlib
components. 'microblaze' is defined as the big-endian version, while
microblazeel is defined as the little-endian version.
config.sub: 2018-07-03
...
| maxq | mb | microblaze | microblazeel | mcore | mep | metag \
...
| microblaze-* | microblazeel-* \
...
microblaze*)
basic_machine=microblaze-xilinx
...
(From OE-Core rev: c052b0c984b28d64527a66ea8e2936ca28b9406f)
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This is beneficial for parted ptests in particular as they
make use of vfat, and fail otherwise.
(From OE-Core rev: ffbc6dc213abf96b816fc9dd87766c3a36935c2a)
Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This helps in booting weston images ( core-image-weston ) with fbdev
backend, without this westons initialization of fbdev backend fails
because it does not get correct frame buffer settings and exits
pre-maturely
(From OE-Core rev: d95b03ae45b36a9b127ef639322e61b21c328d87)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This helps in constructing right arch for target tuple name for
Little-endian ppc
(From OE-Core rev: b6ac40f1cbabb20896bf113568f7735a462ed1a6)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Use wic instead of the live/hddimg filesystem type for x86 machines, as it
produces better filesystems and doesn't have a hard limit of 4GB.
(From OE-Core rev: 04e4e93efa4d8e2bdde950fe95c2fd95f89c13e7)
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Fix the following errors for newlib and baremetal libcs:
ld: unrecognized option '--hash-style=sysv'
ld: unrecognized option '--hash-style=gnu'
(From OE-Core rev: 8ae998fa8dd216d008cc9ddbea98bbb945501e41)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
clang 9.x ( which is now default in meta-clang ) supports riscv
(From OE-Core rev: 198689f74915756ce6ae38d6735780a26e9b3f7e)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
commit 3613b2780a6b5d5d70ea6802be5060a8214cbdb5 from
git://github.com/renesas-rcar/meta-renesas
The renesas rcar SoC H3/M3 is big.LITTLE architecture(cortex-a57.cortex-a53).
In order to optimize the performance of the code running on SoC H3/M3,
add a tune file for ARM Cortex-A53-Cortex-A57.
Create this tune file by refering GCC doc, 3.18.5 ARM Options.
(From OE-Core rev: 7e0c9290a9971b92bcb313742f126ca7488d91c3)
Signed-off-by: Meng Li <Meng.Li@windriver.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Since TUNE_FEATURES now either contains a CPU or an architecture (but
not both) we can't rely on finding the architecture in TUNE_FEATURES.
Use architecture specific over-rides instead.
(From OE-Core rev: 805dd4807d322dc70cef97edd68fdb3142b60fb1)
Signed-off-by: Andre McCurdy <armccurdy@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This allows us to generate a rootFS with a large filesystem for use with
QEMU.
(From OE-Core rev: e06439200e44999c1e2f88d7d6c651da13698ca7)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Default riscv is little-endian moreover most of other arches define
bigendian as tune and treats absense as litteendian, this make risc-v
fall in line
(From OE-Core rev: cd6f377591a7bd7b3c61ce580f997aaeffab3df3)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This helps in defining LE tunes and at the same time specifies
endianness on compiler cmdline clearly, clang e.g. defaults to
little-endian always, so unless specified with -mbig-endian won't
compile the code right
(From OE-Core rev: e0fd699d398f0e88fb208970dea7b74e6e9431fe)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
There was a discussion about what amount of RAM is appropriate for a
default; the outcome was that for now it is still 256M. Some qemu machine
definitions have however set this to 512M so for the sake of
treating all architectures fairly, they are reset back to 256M.
Also runqemu is adjusted to use 256M if QB_MEM is not set at all.
http://lists.openembedded.org/pipermail/openembedded-core/2019-August/285900.html
(From OE-Core rev: 04c01b6cc5be3e6d45d0e04571640648a5655a8b)
Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Configuration:
MACHINE = qemumips64
bitbake lib32-core-image-minimal
runqemu slirp nographic qemumips64 ext4
Error:
ERROR - Failed to run qemu: qemu-system-mips: unable to find CPU model 'MIPS64R2-generic'
Fixed by moving QB_SYSTEM_NAME to Respective configuration file
(From OE-Core rev: e724e8836ed614ff8eaa0d0d9c51d22ee62576b3)
Signed-off-by: Changqing Li <changqing.li@windriver.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Now that we have a -bios option for the RISC-V virt machine in QEMU we
can pass OpenSBI in via -bios and the kernel in via -kernel. We no
longer need to pass the kernel in via -device loader so let's remove
that.
(From OE-Core rev: 65e7f371f19e053d0bac7771a80615f6bada74c7)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Configrations:
MACHINE: qemux86-64
require conf/multilib.conf
MULTILIBS = "multilib:lib32"
DEFAULTTUNE_virtclass-multilib-lib32 = "x86"
Reproduce steps:
bitbake lib32-core-image-minimal
runqemu qemux86-64 nographic lib32-core-image-minimal
Errors:
qemu cannot bootup since:
Booting from ROM...
This kernel requires an x86-64 CPU, but only detected an i686 CPU.
Unable to boot - please use a kernel appropriate for your CPU.
QEMU: Terminated
For lib32 image, override has x86, so the qemubin set to qemu-system-i386,
fix by move QB_SYSTEM_NAME to corresponding conf, don't use the override
(From OE-Core rev: ffaf86f175b2e6caa3a0067f7b3725930b053715)
Signed-off-by: Changqing Li <changqing.li@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
The include is split ready to add the 32-bit RISC-V machine as soon as
glibc supports 32-bit RISC-V.
This is based on the work in the meta-riscv layer, thanks to Khem for
starting this.
(From OE-Core rev: 11b6020dff4550fc3a42e04bc1e86baf37942c62)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
The value of PACKAGE_EXTRA_ARCHS_tune-thunderx should be based on
PACKAGE_EXTRA_ARCHS_tune-armv8a-crc-crypto instead of armv8a-crc-crypto.
Otherwise we would get some sanity check error like this:
OE-core's config sanity checker detected a potential misconfiguration.
Either fix the cause of this error or at your own risk disable the checker (see sanity.conf).
Following is the list of potential problems / advisories:
Error, the PACKAGE_ARCHS variable (all any noarch armv8a-crc-crypto thunderx qemuarm64) for DEFAULTTUNE (thunderx) does not contain TUNE_PKGARCH (aarch64)
(From OE-Core rev: 13cc0f7c0bd98ea228e9bdf51043117d38837ce7)
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This matches what the qemux86_64 is currently using, and
will allow testing the instructions added in the meantime;
particularly various SSE extensions are now enabled.
(From OE-Core rev: f3b1e577ec94c849d0354f5679257f02ef4e4fe9)
Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This makes sure, e.g., ${SOC_FAMILY} and ${MACHINE} have higher
priorities than aarch64.
(From OE-Core rev: 4d1339af88543d85930139dbcb87a669f285ea66)
Signed-off-by: Peter Kjellerstedt <peter.kjellerstedt@axis.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
The armv8a tune specific PACKAGE_EXTRA_ARCHS contained tune feature
names like "crc" and "crypto" rather than package architecture names
like "armv8a-crc" and "armv8a-crypto".
(From OE-Core rev: 1756f2354745ee709886683422887efed4e10dba)
Signed-off-by: Peter Kjellerstedt <peter.kjellerstedt@axis.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
SIMD instructions are a mandatory part of armv8a
(they were optional in armv7a), and the gcc docs
also say that they are always enabled.
(From OE-Core rev: 02288c94e99e9dd444d8c1af186b6d89085b7b8b)
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
armv5 is not a specific tune feature anymore, there is no need to check
it, since having dsp will define if 'e' should be added or not
(From OE-Core rev: 1d6d5bb30a83f9136b7c33e297d48564ae61b50e)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Cc: Peter Kjellerstedt <peter.kjellerstedt@axis.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
For multilib to work correctly, BASE_LIB overrides must be provided.
(From OE-Core rev: b32ec63e48a3552f2e7f3cc5caf61432af716283)
Signed-off-by: teven Hung (洪于玉) <Steven.Hung@mediatek.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
For multilib to work correctly, BASE_LIB overrides must be provided for
each new tune added in this file.
(From OE-Core rev: e39c5ec90ebbc37064c9cd59eba12603317740cd)
Signed-off-by: Mike Crowe <mac@mcrowe.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Some ARM Cortex devices have the VFPv4-D16, but no NEON.
(From OE-Core rev: 594f8584268d5179c18512beada2bae4a21325de)
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
I am not familiar with the big endian, so I don't update it.
I don't have much information about the Cavium ThunderX,
it looks like it supports all the ARM instructions.
(From OE-Core rev: b6c6fa72bdffd5d8995058e8e0e21d5561cc16c6)
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
There are some addtional instructions apart from bare armv8,
also there is armv8.1, armv8.2.
Most the processor would support crc, except X-gene 1.
(From OE-Core rev: d1db78b0e284e1a1f370e71183ded0cbdc1475db)
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
tune files which inherit the arch definitions already define appropriate
-mcpu option, which is equivalent of right -march and -mtune combination
and is preferred since gcc is getting stricter and stricter with option
check semantics and can now find incompatible -march and -mcpu options
better with every release. It does internal feature consistency check
and if it finds out discrepency between what -mcpu would expand to as
compared to -march it will flag the options to be incompatible, for
naked eye it sounds wrong but gcc would translate -mcpu to a given
-march internally and it might not match to what we set in these arch
files.
The effects are quite subtle, where this can result in configure test
failing to compile due to these incompatible options and a feature
option getting disabled for a recipe for no reason.
e.g. with gcc9 which can now detect that -mcpu=cortex-a5 and
-march=armv7-a are incompatible, many features in libstdc++ ends up
disabled due to configure check failures e.g. size_t size, ptrdiff_t
sizes, which inturn results in compiling libstdc++ with unwanted
disabled features.
(From OE-Core rev: ac83d22eb5031f7fdd09d34a1a46d92fd3e39a3c)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
