Fix the following errors for newlib and baremetal libcs:
ld: unrecognized option '--hash-style=sysv'
ld: unrecognized option '--hash-style=gnu'
(From OE-Core rev: 8ae998fa8dd216d008cc9ddbea98bbb945501e41)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
clang 9.x ( which is now default in meta-clang ) supports riscv
(From OE-Core rev: 198689f74915756ce6ae38d6735780a26e9b3f7e)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This allows us to generate a rootFS with a large filesystem for use with
QEMU.
(From OE-Core rev: e06439200e44999c1e2f88d7d6c651da13698ca7)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Default riscv is little-endian moreover most of other arches define
bigendian as tune and treats absense as litteendian, this make risc-v
fall in line
(From OE-Core rev: cd6f377591a7bd7b3c61ce580f997aaeffab3df3)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
There was a discussion about what amount of RAM is appropriate for a
default; the outcome was that for now it is still 256M. Some qemu machine
definitions have however set this to 512M so for the sake of
treating all architectures fairly, they are reset back to 256M.
Also runqemu is adjusted to use 256M if QB_MEM is not set at all.
http://lists.openembedded.org/pipermail/openembedded-core/2019-August/285900.html
(From OE-Core rev: 04c01b6cc5be3e6d45d0e04571640648a5655a8b)
Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Now that we have a -bios option for the RISC-V virt machine in QEMU we
can pass OpenSBI in via -bios and the kernel in via -kernel. We no
longer need to pass the kernel in via -device loader so let's remove
that.
(From OE-Core rev: 65e7f371f19e053d0bac7771a80615f6bada74c7)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
The include is split ready to add the 32-bit RISC-V machine as soon as
glibc supports 32-bit RISC-V.
This is based on the work in the meta-riscv layer, thanks to Khem for
starting this.
(From OE-Core rev: 11b6020dff4550fc3a42e04bc1e86baf37942c62)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
