mirror of
https://git.yoctoproject.org/poky
synced 2026-05-02 09:32:14 +02:00
3c5c4cfa6b
This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
17 lines
401 B
Plaintext
17 lines
401 B
Plaintext
#@TYPE: Machine
|
|
#@NAME: generic riscv32 machine
|
|
#@DESCRIPTION: Machine configuration for running a generic riscv32
|
|
|
|
DEFAULTTUNE ?= "riscv32"
|
|
|
|
require conf/machine/include/riscv/qemuriscv.inc
|
|
|
|
PREFERRED_VERSION_openocd-native = "riscv"
|
|
PREFERRED_VERSION_openocd = "riscv"
|
|
|
|
XVISOR_PLAT = "riscv/virt32"
|
|
|
|
EXTRA_IMAGEDEPENDS += "u-boot"
|
|
UBOOT_MACHINE = "qemu-riscv32_smode_defconfig"
|
|
UBOOT_ELF = "u-boot"
|