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Updating the 4.1 SRCREVs to integrate the following DRM backports: a8abc111a96d drm/i915: Only wait for required lanes in vlv_wait_port_ready() 81354180432b Revert "drm/i915: Hack to tie both common lanes together on chv" d660fc117731 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV 0e797e9cb717 drm/i915: Implement chv display PHY lane stagger setup (From OE-Core rev: 2ea7533b5d45bb459284dd1c3f81d4bcac88f882) Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>