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Updating the 3.19 kernel SRCREVs to integrate the following Braswell changes: 374b5d0e09ea drm/i915: Only wait for required lanes in vlv_wait_port_ready() fca99e8ee111 Revert "drm/i915: Hack to tie both common lanes together on chv" 00682f31b612 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV 654b1a4497c5 drm/i915: Implement chv display PHY lane stagger setup (From OE-Core rev: 211b631b0d7bf4df3152f4d8d626d798d023d512) Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>