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63dffacec4
Currently tested on Zoom2 and Beagle board. Please test if you have an OMAP3 board! The source tree for this recipe is the latest and greatest power management code for OMAP3. You can find it at http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=summary Signed-off-by: Mike Turquette <mturquette@ti.com>
171 lines
5.6 KiB
Diff
171 lines
5.6 KiB
Diff
From be0e1c0f2f529d6f5adb9c5050731d881874c34b Mon Sep 17 00:00:00 2001
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From: Vikram Pandita <vikram.pandita@ti.com>
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Date: Thu, 18 Jun 2009 13:40:08 -0500
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Subject: [PATCH 1/8] OMAP3: MMC: Add mux for pins
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For OMAP3 add MMC1 MMC2 pin mux
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Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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Signed-off-by: Chikkature Rajashekar <madhu.cr@ti.com>
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---
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arch/arm/mach-omap2/devices.c | 42 ++++++++++++++++++++++++++++
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arch/arm/mach-omap2/mux.c | 49 +++++++++++++++++++++++++++++++++
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arch/arm/plat-omap/include/mach/mux.h | 28 +++++++++++++++++++
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3 files changed, 119 insertions(+), 0 deletions(-)
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diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
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index 81f47d9..243815e 100644
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--- a/arch/arm/mach-omap2/devices.c
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+++ b/arch/arm/mach-omap2/devices.c
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@@ -455,6 +455,48 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
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omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
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}
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}
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+
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+ if (cpu_is_omap3430()) {
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+ if (controller_nr == 0) {
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+ omap_cfg_reg(N28_3430_MMC1_CLK);
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+ omap_cfg_reg(M27_3430_MMC1_CMD);
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+ omap_cfg_reg(N27_3430_MMC1_DAT0);
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+ if (mmc_controller->slots[0].wires == 4 ||
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+ mmc_controller->slots[0].wires == 8) {
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+ omap_cfg_reg(N26_3430_MMC1_DAT1);
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+ omap_cfg_reg(N25_3430_MMC1_DAT2);
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+ omap_cfg_reg(P28_3430_MMC1_DAT3);
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+ }
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+ if (mmc_controller->slots[0].wires == 8) {
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+ omap_cfg_reg(P27_3430_MMC1_DAT4);
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+ omap_cfg_reg(P26_3430_MMC1_DAT5);
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+ omap_cfg_reg(R27_3430_MMC1_DAT6);
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+ omap_cfg_reg(R25_3430_MMC1_DAT7);
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+ }
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+ }
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+ if (controller_nr == 1) {
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+ /* MMC2 */
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+ omap_cfg_reg(AE2_3430_MMC2_CLK);
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+ omap_cfg_reg(AG5_3430_MMC2_CMD);
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+ omap_cfg_reg(AH5_3430_MMC2_DAT0);
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+ if (mmc_controller->slots[0].wires == 4 ||
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+ mmc_controller->slots[0].wires == 8) {
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+ omap_cfg_reg(AH4_3430_MMC2_DAT1);
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+ omap_cfg_reg(AG4_3430_MMC2_DAT2);
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+ omap_cfg_reg(AF4_3430_MMC2_DAT3);
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+ }
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+ if (mmc_controller->slots[0].wires == 8)
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+ printk(KERN_WARNING
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+ "\n MMC2: DAT4, DAT5, DAT6, DAT7: "
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+ "Setup the mux in board file");
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+ }
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+ if (controller_nr == 2) {
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+ /* MMC3 */
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+ printk(KERN_WARNING
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+ "\n MMC3: Setup the mux in board file: "
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+ "Multiple options exist, so is board specific");
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+ }
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+ }
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}
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#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
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diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
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index 026c4fc..d49b9a7 100644
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--- a/arch/arm/mach-omap2/mux.c
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+++ b/arch/arm/mach-omap2/mux.c
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@@ -486,6 +486,55 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
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OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
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OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
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+/* MMC1 */
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+MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+
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+/* MMC2 */
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+MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
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+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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+
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+/* MMC3 */
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+MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
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+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
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+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
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+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
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+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
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+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
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+MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
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+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
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};
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#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
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diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
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index 85a6217..d24fdf9 100644
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--- a/arch/arm/plat-omap/include/mach/mux.h
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+++ b/arch/arm/plat-omap/include/mach/mux.h
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@@ -853,6 +853,34 @@ enum omap34xx_index {
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AE5_34XX_GPIO143,
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H19_34XX_GPIO164_OUT,
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J25_34XX_GPIO170,
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+
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+ /* MMC1 */
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+ N28_3430_MMC1_CLK,
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+ M27_3430_MMC1_CMD,
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+ N27_3430_MMC1_DAT0,
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+ N26_3430_MMC1_DAT1,
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+ N25_3430_MMC1_DAT2,
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+ P28_3430_MMC1_DAT3,
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+ P27_3430_MMC1_DAT4,
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+ P26_3430_MMC1_DAT5,
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+ R27_3430_MMC1_DAT6,
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+ R25_3430_MMC1_DAT7,
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+
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+ /* MMC2 */
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+ AE2_3430_MMC2_CLK,
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+ AG5_3430_MMC2_CMD,
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+ AH5_3430_MMC2_DAT0,
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+ AH4_3430_MMC2_DAT1,
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+ AG4_3430_MMC2_DAT2,
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+ AF4_3430_MMC2_DAT3,
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+
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+ /* MMC3 */
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+ AF10_3430_MMC3_CLK,
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+ AC3_3430_MMC3_CMD,
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+ AE11_3430_MMC3_DAT0,
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+ AH9_3430_MMC3_DAT1,
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+ AF13_3430_MMC3_DAT2,
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+ AF13_3430_MMC3_DAT3,
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};
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struct omap_mux_cfg {
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--
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1.6.3.2
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