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4d6a9708e6
This is a combined backport from upstream patches for added risc-v support Upstream code has been re-organised before risc-v support was added to its mix of two commits primarily171b533800680a752c83(From OE-Core rev: 7356ae622bd71ba1a022a9ed18c4cf085e948b38) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
46 lines
1.4 KiB
Diff
46 lines
1.4 KiB
Diff
From 4a6ace0a965965ea15e88c3418c7158ca5cc9f8f Mon Sep 17 00:00:00 2001
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From: Khem Raj <raj.khem@gmail.com>
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Date: Thu, 21 Nov 2019 10:12:05 -0800
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Subject: [PATCH] architecture: Recognise RISCV-32/RISCV-64
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Upstream-Status: Backport [https://github.com/systemd/systemd/commit/171b53380085b1288b03b19a2b978f36a5c003d0]
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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src/architecture.h | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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diff --git a/src/architecture.h b/src/architecture.h
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index 26679e2..89c7d32 100644
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--- a/src/architecture.h
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+++ b/src/architecture.h
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@@ -57,6 +57,8 @@ enum {
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ARCHITECTURE_M68K,
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ARCHITECTURE_TILEGX,
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ARCHITECTURE_CRIS,
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+ ARCHITECTURE_RISCV32,
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+ ARCHITECTURE_RISCV64,
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_ARCHITECTURE_MAX,
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_ARCHITECTURE_INVALID = -1
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};
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@@ -194,6 +196,17 @@ int uname_architecture(void);
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#elif defined(__cris__)
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# define native_architecture() ARCHITECTURE_CRIS
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# error "Missing LIB_ARCH_TUPLE for CRIS"
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+#elif defined(__riscv)
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+# if __SIZEOF_POINTER__ == 4
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+# define native_architecture() ARCHITECTURE_RISCV32
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+# define LIB_ARCH_TUPLE "riscv32-linux-gnu"
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+# elif __SIZEOF_POINTER__ == 8
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+# define native_architecture() ARCHITECTURE_RISCV64
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+# define LIB_ARCH_TUPLE "riscv64-linux-gnu"
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+# else
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+# error "Unrecognized riscv architecture variant"
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+# endif
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+# define PROC_CPUINFO_MODEL "cpu model"
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#else
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# error "Please register your architecture here!"
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#endif
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--
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2.24.0
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