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97bb9c5b67
These are fixes mainly cherrypicks for mips/ppc/x86 mainly fixing PRs in ld and gold (From OE-Core rev: f098cfc24bae8e0685bcae53ea4fdc3326ddc6c4) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
Upstream-Status: Backport
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From 97beee82f0e45e65308083a7e4cfaab57623733c Mon Sep 17 00:00:00 2001
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From: cltang <cltang>
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Date: Mon, 19 Dec 2011 10:34:15 +0000
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Subject: [PATCH 035/262] 2011-12-19 Chung-Lin Tang
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<cltang@codesourcery.com>
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Backport from mainline:
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2011-12-13 Chung-Lin Tang <cltang@codesourcery.com>
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* elfxx-mips.c (mips_elf_calculate_relocation): Correct
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R_MIPS16_HI16/R_MIPS16_LO16 handling of two cleared lower bits,
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update comments.
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diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
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index 6b908ad..3939183 100644
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--- a/bfd/elfxx-mips.c
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+++ b/bfd/elfxx-mips.c
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@@ -5531,10 +5531,11 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
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12: addu $v0,$v1
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14: move $gp,$v0
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So the offsets of hi and lo relocs are the same, but the
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- $pc is four higher than $t9 would be, so reduce
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- both reloc addends by 4. */
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+ base $pc is that used by the ADDIUPC instruction at $t9 + 4.
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+ ADDIUPC clears the low two bits of the instruction address,
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+ so the base is ($t9 + 4) & ~3. */
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if (r_type == R_MIPS16_HI16)
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- value = mips_elf_high (addend + gp - p - 4);
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+ value = mips_elf_high (addend + gp - ((p + 4) & ~(bfd_vma) 0x3));
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/* The microMIPS .cpload sequence uses the same assembly
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instructions as the traditional psABI version, but the
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incoming $t9 has the low bit set. */
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@@ -5557,7 +5558,7 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
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/* See the comment for R_MIPS16_HI16 above for the reason
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for this conditional. */
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if (r_type == R_MIPS16_LO16)
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- value = addend + gp - p;
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+ value = addend + gp - (p & ~(bfd_vma) 0x3);
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else if (r_type == R_MICROMIPS_LO16
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|| r_type == R_MICROMIPS_HI0_LO16)
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value = addend + gp - p + 3;
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--
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1.7.9.5
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