mirror of
https://git.yoctoproject.org/poky
synced 2026-03-19 13:49:41 +01:00
u-boot: Dynamic RISC-V ISA configuration
Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections
via config fragments.
This allows the following items to be selected dynamically:
CONFIG_RISCV_ISA_C
CONFIG_RISCV_ISA_F
CONFIG_RISCV_ISA_D
CONFIG_RISCV_ISA_ZBB
CONFIG_RISCV_ISA_A
CONFIG_RISCV_ISA_ZICBOM
(From OE-Core rev: de890297b392fcf7f5bd2d25d3c173373b93dd36)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Signed-off-by: Antonin Godard <antonin.godard@bootlin.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
committed by
Richard Purdie
parent
f4f2cdb39b
commit
7c354e6e24
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
Normal file
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
Normal file
@@ -0,0 +1 @@
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
Normal file
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
Normal file
@@ -0,0 +1 @@
|
||||
CONFIG_RISCV_ISA_C=y
|
||||
6
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
Normal file
6
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
Normal file
@@ -0,0 +1,6 @@
|
||||
# CONFIG_RISCV_ISA_C is not set
|
||||
# CONFIG_RISCV_ISA_F is not set
|
||||
# CONFIG_RISCV_ISA_D is not set
|
||||
# CONFIG_RISCV_ISA_ZBB is not set
|
||||
# CONFIG_RISCV_ISA_A is not set
|
||||
# CONFIG_RISCV_ISA_ZICBOM is not set
|
||||
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
Normal file
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
Normal file
@@ -0,0 +1 @@
|
||||
CONFIG_RISCV_ISA_D=y
|
||||
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
Normal file
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
Normal file
@@ -0,0 +1 @@
|
||||
CONFIG_RISCV_ISA_F=y
|
||||
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
Normal file
1
meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
Normal file
@@ -0,0 +1 @@
|
||||
CONFIG_RISCV_ISA_ZBB=y
|
||||
@@ -0,0 +1 @@
|
||||
CONFIG_RISCV_ISA_ZICBOM=y
|
||||
@@ -16,6 +16,18 @@ SRCREV = "34820924edbc4ec7803eb89d9852f4b870fa760a"
|
||||
|
||||
SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master;tag=v${PV}"
|
||||
|
||||
SRC_URI_RISCV = "\
|
||||
file://u-boot-riscv-isa_clear.cfg \
|
||||
${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \
|
||||
${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \
|
||||
${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \
|
||||
${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \
|
||||
${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \
|
||||
"
|
||||
|
||||
SRC_URI:append:riscv32 = "${SRC_URI_RISCV}"
|
||||
SRC_URI:append:riscv64 = "${SRC_URI_RISCV}"
|
||||
|
||||
B = "${WORKDIR}/build"
|
||||
|
||||
inherit pkgconfig
|
||||
|
||||
Reference in New Issue
Block a user