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qemu: add 34Kf-64tlb fictitious cpu type
In Yocto Project PR 13992 it was reported that qemumips in autobuilder runs almost twice slower then qemumips64 and some times hit time out. Upon investigations of qemu-system with perf, gdb, and SystemTap and comparing qemumips and qemumips64 machines behavior it was noticed that qemu soft mmu code behaves quite different and in case if qemumips tlbwr instruction called 16 times more oftern. It happens that in qemumips64 case qemu runs with cpu type that contains 64 TLB, but in case of qemumips qemu runs with cpu type that contains only 16 TLBs. The idea of proposed qemu patch is to introduce fictitious 34Kf-64tlb cpu type that defined exactly as 34Kf but has 64 TLBs, instead of original 16 TLBs. Testing of core-image-full-cmdline:do_testimage with 34Kf-64tlb shows 40% or so test execution real time improvement. Note for future porters of the patch: easiest way to update the patch and be in sync with 34Kf definition is to copy 34Kf machine definition and apply the following changes to it (just change 15 to 63 of CP0C1_MMU bits value) [kamensky@coreos-lnx2 qemu]$ diff ~/34Kf.c ~/34Kf-64tlb.c 2c2 < .name = "34Kf", > .name = "34Kf-64tlb", 6c6 < .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | > .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | Fixes https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 Upstream Status: Inappropriate (From OE-Core rev: 4470a04943352224955f17e004962f0f9e1c9b0c) Signed-off-by: Victor Kamensky <kamensky@cisco.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Victor Kamensky
committed by
Richard Purdie
Richard Purdie
parent
fe74a4edd2
commit
f6f5d09205
@@ -31,6 +31,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
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file://0001-qemu-Do-not-include-file-if-not-exists.patch \
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file://find_datadir.patch \
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file://usb-fix-setup_len-init.patch \
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file://0001-mips-add-34Kf-64tlb-fictitious-cpu-type-like-34Kf-bu.patch \
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"
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UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
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@@ -0,0 +1,118 @@
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From b3fcc7d96523ad8e3ea28c09d495ef08529d01ce Mon Sep 17 00:00:00 2001
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From: Victor Kamensky <kamensky@cisco.com>
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Date: Wed, 7 Oct 2020 10:19:42 -0700
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Subject: [PATCH] mips: add 34Kf-64tlb fictitious cpu type like 34Kf but with
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64 TLBs
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In Yocto Project CI runs it was observed that test run
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of 32 bit mips image takes almost twice longer than 64 bit
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mips image with the same logical load and CI execution
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hits timeout.
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See https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
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Yocto project uses 34Kf cpu type to run 32 bit mips image,
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and MIPS64R2-generic cpu type to run 64 bit mips64 image.
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Upon qemu behavior differences investigation between mips
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and mips64 two prominent observations came up: under
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logically similar load (same definition and configuration
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of user-land image) in case of mips get_physical_address
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function is called almost twice more often, meaning
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twice more memory accesses involved in this case. Also
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number of tlbwr instruction executed (r4k_helper_tlbwr
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qemu function) almost 16 time bigger in mips case than in
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mips64.
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It turns out that 34Kf cpu has 16 TLBs, but in case of
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MIPS64R2-generic it is 64 TLBs. So that explains why
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some many more tlbwr had to be execute by kernel TLB refill
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handler in case of 32 bit misp.
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The idea of the fix is to come up with new 34Kf-64tlb fictitious
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cpu type, that would behave exactly as 34Kf but it would
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contain 64 TLBs to reduce TLB trashing. After all, adding
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more TLBs to soft mmu is easy.
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Experiment with some significant non-trvial load in Yocto
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environment by running do_testimage load shows that 34Kf-64tlb
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cpu performs 40% or so better than original 34Kf cpu wrt test
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execution real time.
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It is not ideal to have cpu type that does not exist in the
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wild but given performance gains it seems to be justified.
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Signed-off-by: Victor Kamensky <kamensky@cisco.com>
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---
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target/mips/translate_init.inc.c | 55 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 55 insertions(+)
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diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
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index 637caccd89..b73ab48231 100644
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--- a/target/mips/translate_init.inc.c
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+++ b/target/mips/translate_init.inc.c
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@@ -297,6 +297,61 @@ const mips_def_t mips_defs[] =
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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.mmu_type = MMU_TYPE_R4000,
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},
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+ /*
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+ * Verbatim copy of "34Kf" cpu, only bumped up number of TLB entries
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+ * from 16 to 64 (see CP0_Config0 value at CP0C1_MMU bits) to improve
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+ * performance by reducing number of TLB refill exceptions and
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+ * eliminating need to run all corresponding TLB refill handling
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+ * instructions.
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+ */
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+ {
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+ .name = "34Kf-64tlb",
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+ .CP0_PRid = 0x00019500,
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+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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+ (MMU_TYPE_R4000 << CP0C0_MT),
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+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
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+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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+ (1 << CP0C1_CA),
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+ .CP0_Config2 = MIPS_CONFIG2,
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+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
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+ (1 << CP0C3_DSPP),
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+ .CP0_LLAddr_rw_bitmask = 0,
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+ .CP0_LLAddr_shift = 0,
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+ .SYNCI_Step = 32,
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+ .CCRes = 2,
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+ .CP0_Status_rw_bitmask = 0x3778FF1F,
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+ .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
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+ (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
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+ (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
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+ (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
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+ (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
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+ (0xff << CP0TCSt_TASID),
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+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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+ (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
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+ .CP1_fcr31 = 0,
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+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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+ .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
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+ .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
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+ .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
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+ (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
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+ .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
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+ .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
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+ (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
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+ .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
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+ .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
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+ (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
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+ .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
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+ .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
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+ (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
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+ .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
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+ .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
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+ (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
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+ .SEGBITS = 32,
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+ .PABITS = 32,
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+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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+ .mmu_type = MMU_TYPE_R4000,
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+ },
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{
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.name = "74Kf",
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.CP0_PRid = 0x00019700,
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--
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2.14.5
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