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This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
123 lines
4.5 KiB
Plaintext
123 lines
4.5 KiB
Plaintext
2025/06/08 - Mark Hatle <mark.hatle@amd.com>
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- Initial Revision
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The RISC-V ISA is broken into two parts, a base ISA and extensions. As
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of the writing of this document these are documented at:
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https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications
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Specifically "The RISC-V Instruction Set Manual Volume I: Unprivileged ISA"
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was used to create this implementation.
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Requirements
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------------
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As RISC-V is a “variable” ISA (a base isa plus numerous extensions), a
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mechanism is required to specify a series of ISA features that a user or
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tune can use to specify a specific CPU instantiation.
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Not all ratified or draft features should or can be implemented with the
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available resources.
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The implementation should work for Linux, baremetal (newlib), zephyr and
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other operating systems. Supported extensions should be based on
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real-world examples.
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Linux
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-----
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Linux required base and support extensions should be available. Linux
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requires:
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* Base: rv32ima & rv64ima
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* Optional FPU: fd
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* Optional RISCV_ISA_C: c
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* Optiona RISCV_ISA_V: v
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* Required additional: _zicsr_zifencei
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* Optional RISCV_ISA_ZBA: _zba
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* Optional RISCV_ISA_ZBB: _zbb
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* Optional RISCV_ISA_ZBC: _zbc (not supported by current QEMU design)
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See: https://git.yoctoproject.org/linux-yocto/tree/arch/riscv/Makefile?h=v6.12/base
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Baremetal
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---------
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AMD Microblaze-V FPGA support uses the following static configurations:
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Base: rv32e, rv32i, rv64i
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Extensions: m, a, f, d, c, b, zicsr, zifencei
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Zephyr
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------
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AMD Microblaze-V development for Zephyr is the same as Baremetal, with a
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few additional extensions: zbc, zicbom
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ABI
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---
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The following ABIs are supported GNU tools and some combination of systems.
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* ilp32 - Integer, long and pointer are 32-bit
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* lp64 - Long and pointer are 64-bit (integer is 32-bit)
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The ABI is dependent upon the core system implementation, as ilp32 can
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only used on an ‘rv32’ system, while lp64 can only be used on an ‘rv64’
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system.
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There are additional variations of each ABI:
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* e - used with the Reduced register extension
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* f - used when single precision floating point (but not double precision) is
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enabled
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* d - used when both single and double precision floating point is enabled
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Based on the above, the ABI should be automatically determined based on
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the selected Base ISA and Extensions.
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Implementation
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--------------
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To make it easier to generate the RISC-V canonical arch, ISA based -march,
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and the ABI string, a few new variables are added for specific RISC-V items.
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TUNE_RISCV_ARCH - This contains the canonical GNU style arch, generally this
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will evaluate to "riscv32" or "riscv64".
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TUNE_RISCV_MARCH - This will contain an ISA based -march string compatible
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with gcc and similar toolchains. For example:
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rv32imacfd_zicsr_zifencei
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TUNE_RISCV_ABI - This is the generated ABI that corresponds to the ARCH and
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MARCH/ISA values. For riscv32, the value will be ilp32
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(int, long and pointer is 32-bit) with the ISA
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variation. For riscv64, the value will be lp64 (long
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and pointer are 64-bit bit, while int is 32-bit) with the
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ISA variation. The ISA affects the ABI when the 'e', 'f'
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and 'd' extension are used.
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TUNE_RISCV_PKGARCH - This is the generated PKGARCH value.
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The standard variables are defined as:
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TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}"
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The above will allow the user to specify an implementation specific
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TUNE_CCARGS for a given processor tune if the default implementtion is
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not adequate for some reason. It is expected that most, if not all,
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implementations will use the default behavior.
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TUNE_ARCH = "${TUNE_RISCV_ARCH}"
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TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}"
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The above two will always base their setting off the standard TUNE_FEATURES.
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Ratified and draft extensions should be implemented as TUNE_FEATURES in
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the arch-riscv.inc file.
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Vendor specific extensions and processor specific settings should go
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into a 'tune-<vendor>.inc' file, with tune-riscv.inc being reserved for
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general purpose tunes.
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TUNE_FEATURE Helper
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-------------------
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A special helper function has been written that will convert RISC-V ISA
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notation into TUNE_FEATURE notion, for example:
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rv32g -> rv 32 i m a f d zicsr zifencei
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The helper can be called using oe.tune.riscv_isa_to_tune("<ISA>") such as
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oe.tune.riscv_isa_to_tune("rv64gc") which would return:
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rv 64 i m a f d c zicsr zifencei
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